Job Description Summary

GE Vernova’s Power Conversion & Storage business combines advanced energy conversion and storage systems to meet the electrification needs of utilities and industries. With a focus on power stability, energy storage and industrial electrification solutions, Power Conversion & Storage empowers customers by addressing their most complex electrification challenges and accelerating their transition to a sustainable, decarbonized future.

Job Description

Roles and Responsibilities

• Design and implement robust C software libraries for CPU control of medium voltage converters
• Develop real-time DSP runtime and application-level code for performance-optimized operation
• Architect embedded software systems using FPGA technology to meet timing and functional requirements
• Create technical documentation including integration guidelines, user manuals, and interface specifications
• Design control electronics schematics and PCB layouts, incorporating PLDs and FPGAs for power converter applications

Required Qualifications

• Master's degree in Electrical or Computer or Software Engineering, with a minimum of 3 years of post-academic embedded systems experience
• OR Bachelor’s degree with a minimum of 5 years of post-academic embedded systems experience in an industrial setting

Desired Characteristics

• Proficient in communication protocols (e.g., EtherCAT, EGD, Modbus)
• Solid understanding of real-time operating systems (RTOS) such as VxWorks or Linux Red Hat
• Advanced experience in VHDL programming for FPGAs (Xilinx and Intel), including Quartus, Vivado, and simulation tools like ModelSim/Questa
• Competent in hardware design tools: Altium Designer, PSpice; experience with verification methodologies including SystemVerilog and UVM
• Willingness to travel for technical collaboration, integration, and support activities
• Team-oriented, proactive, and receptive to diverse and fast-paced engineering environments
• Demonstrated autonomy and intellectual curiosity—ability to learn and apply new tools and architectures
• Experience mentoring or coaching junior engineers in embedded development workflows
• Foundational understanding of power electronics, converter topologies, and system-level behavior in MV environments
• Motivated by solving complex engineering challenges that push technology boundaries in mission-critical applications

 

 

For candidates applying to a U.S. based position, the pay range for this position is between $88,600.00 and $147,600.00. The Company pays a geographic differential of 110%, 120% or 130% of salary in certain areas. The specific pay offered may be influenced by a variety of factors, including the candidate’s experience, education, and skill set.

 

 

Bonus eligibility: discretionary annual bonus.

 

 

This posting is expected to remain open for at least seven days after it was posted on December 01, 2025.

 

 

Available benefits include medical, dental, vision, and prescription drug coverage; access to Health Coach from GE Vernova, a 24/7 nurse-based resource; and access to the Employee Assistance Program, providing 24/7 confidential assessment, counseling and referral services. Retirement benefits include the GE Vernova Retirement Savings Plan, a tax-advantaged 401(k) savings opportunity with company matching contributions and company retirement contributions, as well as access to Fidelity resources and financial planning consultants. Other benefits include tuition assistance, adoption assistance, paid parental leave, disability benefits, life insurance, 12 paid holidays, and permissive time off.

 

 

GE Vernova Inc. or its affiliates (collectively or individually, “GE Vernova”) sponsor certain employee benefit plans or programs GE Vernova reserves the right to terminate, amend, suspend, replace, or modify its benefit plans and programs at any time and for any reason, in its sole discretion. No individual has a vested right to any benefit under a GE Vernova welfare benefit plan or program. This document does not create a contract of employment with any individual.